FifoWrFsm.rtl Architecture Reference

Architecture >> FifoWrFsm::rtl

Processes
comb	( din , r , rdIndex , rdRdy , wr_en )
seq	( rst , wr_clk )
seq	( wr_clk )
comb	( din , r , rdIndex , rdRdy , wr_en )
seq	( rst , wr_clk )
seq	( wr_clk )

Constants
FULL_C	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 1 ' )
AFULL_C	slv ( ADDR_WIDTH_G- 1 downto 0 ) := FULL_C- 1
REG_INIT_C	RegType := ( wrRdy = > ite ( FIFO_ASYNC_G , ' 0 ' , ' 1 ' ) , wr_ack = > ' 0 ' , overflow = > ' 0 ' , prog_full = > ' 1 ' , almost_full = > ' 1 ' , full = > ' 1 ' , not_full = > ' 0 ' , count = > ( others = > ' 1 ' ) , wrAddr = > ( others = > ' 0 ' ) , wrIndex = > ( others = > ' 0 ' ) )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• base/fifo/rtl/inferred/FifoWrFsm.vhd
• build/SRC_VHDL/surf/FifoWrFsm.vhd