Caui4GtyIpWrapper Entity Reference

Inheritance diagram for Caui4GtyIpWrapper:

Collaboration diagram for Caui4GtyIpWrapper:

Entities
Caui4GtyIpWrapper.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>

Generics
TPD_G	time := 1 ns
SIM_SPEEDUP_G	boolean := false
REFCLK_TYPE_G	boolean := true
MAX_PAYLOAD_SIZE_G	positive := 8192

Ports
stableClk	in	sl
stableRst	in	sl
phyClk	out	sl
phyRst	out	sl
phyRxMaster	out	AxiStreamMasterType
phyTxMaster	in	AxiStreamMasterType
phyTxSlave	out	AxiStreamSlaveType
phyReady	out	sl
loopback	in	slv ( 2 downto 0 ) := ( others = > ' 0 ' )
rxPolarity	in	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
txPolarity	in	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
txDiffCtrl	in	Slv5Array ( 3 downto 0 ) := ( others = > " 11000 " )
txPreCursor	in	Slv5Array ( 3 downto 0 ) := ( others = > " 00000 " )
txPostCursor	in	Slv5Array ( 3 downto 0 ) := ( others = > " 00000 " )
gtRefClkP	in	sl
gtRefClkN	in	sl
gtRxP	in	slv ( 3 downto 0 )
gtRxN	in	slv ( 3 downto 0 )
gtTxP	out	slv ( 3 downto 0 )
gtTxN	out	slv ( 3 downto 0 )

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The documentation for this design unit was generated from the following file:

• ethernet/Caui4Core/gtyUltraScale+/rtl/Caui4GtyIpWrapper.vhd