Architecture >> Caui4GtyIpWrapper::mapping

Processes
RX_AXIS	( txusrclk2 )
comb	( r , stat_rx_aligned , stat_rx_rsfec_uncorrected_cw_inc , usr_rx_reset )
seq	( txusrclk2 )

Constants
TX_FIFO_ADDR_WIDTH_C	positive := log2 ( MAX_PAYLOAD_SIZE_G/ 64 ) + 1
REG_INIT_C	RegType := ( phyRdy = > ' 0 ' , ctl_rx_enable = > ' 0 ' , ctl_tx_enable = > ' 0 ' , ctl_tx_send_rfi = > ' 0 ' , state = > INIT_S )

Types
StateType	( INIT_S , WAIT_S , DONE_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
txusrclk2	sl
usr_tx_reset	sl
usr_rx_reset	sl
stat_rx_aligned	sl
stat_rx_rsfec_uncorrected_cw_inc	sl
stat_rx_rsfec_corrected_cw_inc	sl
phyClock	sl
phyReset	sl
gtLoopback	slv ( 11 downto 0 )
gtTxdiffctrl	slv ( 19 downto 0 )
gtTxPreCursor	slv ( 19 downto 0 )
gtTxPostCursor	slv ( 19 downto 0 )
stableReset	sl
rxAxis	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
rxMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
txMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
txSlave	AxiStreamSlaveType

Records
RegType

Instantiations
u_pwruprst	PwrUpRst <Entity PwrUpRst>
u_phyclk	ClockManagerUltraScale <Entity ClockManagerUltraScale>
u_rx_fifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_tx_fifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_caui4	caui4gtyipcore156mhz
u_caui4	caui4gtyipcore161mhz
u_syncbits	Synchronizer <Entity Synchronizer>
u_rxfeccorinc	SynchronizerOneShot <Entity SynchronizerOneShot>
u_rxfecuncorinc	SynchronizerOneShot <Entity SynchronizerOneShot>

The documentation for this design unit was generated from the following file:

Processes

Components