ClockManagerUltraScale Entity Reference

Inheritance diagram for ClockManagerUltraScale:

Collaboration diagram for ClockManagerUltraScale:

Entities
ClockManagerUltraScale.rtl	architecture

Libraries
ieee
unisim
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
vcomponents
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
SIMULATION_G	boolean := false
TYPE_G	string := " MMCM "
INPUT_BUFG_G	boolean := true
FB_BUFG_G	boolean := true
RST_IN_POLARITY_G	sl := ' 1 '
NUM_CLOCKS_G	integer range 1 to 7
BANDWIDTH_G	string := " OPTIMIZED "
CLKIN_PERIOD_G	real := 10 . 0
DIVCLK_DIVIDE_G	integer range 1 to 106 := 1
CLKFBOUT_MULT_F_G	real range 1 . 0 to 128 . 0 := 1 . 0
CLKFBOUT_MULT_G	integer range 1 to 19 := 5
CLKOUT0_DIVIDE_F_G	real range 1 . 0 to 128 . 0 := 1 . 0
CLKOUT0_DIVIDE_G	integer range 1 to 128 := 1
CLKOUT1_DIVIDE_G	integer range 1 to 128 := 1
CLKOUT2_DIVIDE_G	integer range 1 to 128 := 1
CLKOUT3_DIVIDE_G	integer range 1 to 128 := 1
CLKOUT4_DIVIDE_G	integer range 1 to 128 := 1
CLKOUT5_DIVIDE_G	integer range 1 to 128 := 1
CLKOUT6_DIVIDE_G	integer range 1 to 128 := 1
CLKOUT0_PHASE_G	real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT1_PHASE_G	real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT2_PHASE_G	real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT3_PHASE_G	real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT4_PHASE_G	real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT5_PHASE_G	real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT6_PHASE_G	real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT0_DUTY_CYCLE_G	real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT1_DUTY_CYCLE_G	real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT2_DUTY_CYCLE_G	real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT3_DUTY_CYCLE_G	real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT4_DUTY_CYCLE_G	real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT5_DUTY_CYCLE_G	real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT6_DUTY_CYCLE_G	real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT0_RST_HOLD_G	integer range 3 to ( 2 ** 24 ) := 3
CLKOUT1_RST_HOLD_G	integer range 3 to ( 2 ** 24 ) := 3
CLKOUT2_RST_HOLD_G	integer range 3 to ( 2 ** 24 ) := 3
CLKOUT3_RST_HOLD_G	integer range 3 to ( 2 ** 24 ) := 3
CLKOUT4_RST_HOLD_G	integer range 3 to ( 2 ** 24 ) := 3
CLKOUT5_RST_HOLD_G	integer range 3 to ( 2 ** 24 ) := 3
CLKOUT6_RST_HOLD_G	integer range 3 to ( 2 ** 24 ) := 3
CLKOUT0_RST_POLARITY_G	sl := ' 1 '
CLKOUT1_RST_POLARITY_G	sl := ' 1 '
CLKOUT2_RST_POLARITY_G	sl := ' 1 '
CLKOUT3_RST_POLARITY_G	sl := ' 1 '
CLKOUT4_RST_POLARITY_G	sl := ' 1 '
CLKOUT5_RST_POLARITY_G	sl := ' 1 '
CLKOUT6_RST_POLARITY_G	sl := ' 1 '

Ports
clkIn	in	sl
rstIn	in	sl := ' 0 '
clkOut	out	slv ( NUM_CLOCKS_G- 1 downto 0 )
rstOut	out	slv ( NUM_CLOCKS_G- 1 downto 0 )
locked	out	sl
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd
• xilinx/UltraScale/clocking/rtl/ClockManagerUltraScale.vhd