ClockManagerUltraScale.rtl Architecture Reference

Architecture >> ClockManagerUltraScale::rtl

Constants
RST_HOLD_C	IntegerArray ( 0 to 6 ) := ( CLKOUT0_RST_HOLD_G , CLKOUT1_RST_HOLD_G , CLKOUT2_RST_HOLD_G , CLKOUT3_RST_HOLD_G , CLKOUT4_RST_HOLD_G , CLKOUT5_RST_HOLD_G , CLKOUT6_RST_HOLD_G )
RST_POLARITY_C	slv ( 0 to 6 ) := ( CLKOUT0_RST_POLARITY_G , CLKOUT1_RST_POLARITY_G , CLKOUT2_RST_POLARITY_G , CLKOUT3_RST_POLARITY_G , CLKOUT4_RST_POLARITY_G , CLKOUT5_RST_POLARITY_G , CLKOUT6_RST_POLARITY_G )
CLKOUT0_DIVIDE_F_C	real := ite ( CLKOUT0_DIVIDE_F_G = 1 . 0 , real ( CLKOUT0_DIVIDE_G ) , CLKOUT0_DIVIDE_F_G )
CLKFBOUT_MULT_F_C	real := ite ( CLKFBOUT_MULT_F_G = 1 . 0 , real ( CLKFBOUT_MULT_G ) , CLKFBOUT_MULT_F_G )

Signals
rstInLoc	sl
clkInLoc	sl
lockedLoc	sl
clkOutMmcm	slv ( 6 downto 0 ) := ( others = > ' 0 ' )
clkOutLoc	slv ( 6 downto 0 ) := ( others = > ' 0 ' )
clkFbOut	sl
clkFbIn	sl
drpRdy	sl
drpEn	sl
drpWe	sl
drpAddr	slv ( 6 downto 0 )
drpDi	slv ( 15 downto 0 )
drpDo	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
drpDo01	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
clkOutMmcm	slv ( 6 downto 0 )
clkOutLoc	slv ( 6 downto 0 )
drpDo	slv ( 15 downto 0 )

Attributes
keep_hierarchy	string
keep_hierarchy	architecture is " yes "

Instantiations
u_axilitetodrp	AxiLiteToDrp <Entity AxiLiteToDrp>
u_mmcm	mmcme4_adv
u_mmcm	MmcmEmulation <Entity MmcmEmulation>
u_pll	plle4_adv
u_pll	MmcmEmulation <Entity MmcmEmulation>
u_bufg	bufg
u_bufg	bufg
u_bufg	bufg
rstsync_1	RstSync <Entity RstSync>
u_axilitetodrp	AxiLiteToDrp <Entity AxiLiteToDrp>
u_mmcm	mmcme3_adv
u_mmcm	MmcmEmulation <Entity MmcmEmulation>
u_pll	plle3_adv
u_pll	MmcmEmulation <Entity MmcmEmulation>
u_bufg	bufg
u_bufg	bufg
u_bufg	bufg
rstsync_1	RstSync <Entity RstSync>

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The documentation for this design unit was generated from the following files:

• xilinx/UltraScale+/clocking/rtl/ClockManagerUltraScale.vhd
• xilinx/UltraScale/clocking/rtl/ClockManagerUltraScale.vhd