AxiLiteToDrp Entity Reference

Inheritance diagram for AxiLiteToDrp:

Collaboration diagram for AxiLiteToDrp:

Entities
AxiLiteToDrp.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
COMMON_CLK_G	boolean := false
EN_ARBITRATION_G	boolean := false
TIMEOUT_G	positive := 4096
ADDR_WIDTH_G	positive range 1 to 32 := 16
DATA_WIDTH_G	positive range 1 to 32 := 16

Ports
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
drpClk	in	sl
drpRst	in	sl
drpGnt	in	sl := ' 1 '
drpReq	out	sl
drpRdy	in	sl
drpEn	out	sl
drpWe	out	sl
drpUsrRst	out	sl
drpAddr	out	slv ( ADDR_WIDTH_G- 1 downto 0 )
drpDi	out	slv ( DATA_WIDTH_G- 1 downto 0 )
drpDo	in	slv ( DATA_WIDTH_G- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• axi/bridge/rtl/AxiLiteToDrp.vhd
• build/SRC_VHDL/surf/AxiLiteToDrp.vhd