AxiLiteToDrp.rtl Architecture Reference

Architecture >> AxiLiteToDrp::rtl

Processes
comb	( drpDo , drpGnt , drpRdy , drpRst , r , readMaster , writeMaster )
seq	( drpClk )
comb	( drpDo , drpGnt , drpRdy , drpRst , r , readMaster , writeMaster )
seq	( drpClk )

Constants
REG_INIT_C	RegType := ( drpUsrRst = > ' 1 ' , drpReq = > ' 0 ' , drpEn = > ' 0 ' , drpWe = > ' 0 ' , drpAddr = > ( others = > ' 0 ' ) , drpDi = > ( others = > ' 0 ' ) , timer = > 0 , writeSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , readSlave = > AXI_LITE_READ_SLAVE_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , REQ_S , ACK_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
readMaster	AxiLiteReadMasterType
readSlave	AxiLiteReadSlaveType
writeMaster	AxiLiteWriteMasterType
writeSlave	AxiLiteWriteSlaveType

Records
RegType

Instantiations
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>

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The documentation for this design unit was generated from the following files:

• axi/bridge/rtl/AxiLiteToDrp.vhd
• build/SRC_VHDL/surf/AxiLiteToDrp.vhd