AxiLiteAsync Entity Reference

Inheritance diagram for AxiLiteAsync:

Collaboration diagram for AxiLiteAsync:

Entities
AxiLiteAsync.STRUCTURE	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
AXI_ERROR_RESP_G	slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
COMMON_CLK_G	boolean := false
NUM_ADDR_BITS_G	natural := 32
PIPE_STAGES_G	integer range 0 to 16 := 0

Ports
sAxiClk	in	sl
sAxiClkRst	in	sl
sAxiReadMaster	in	AxiLiteReadMasterType
sAxiReadSlave	out	AxiLiteReadSlaveType
sAxiWriteMaster	in	AxiLiteWriteMasterType
sAxiWriteSlave	out	AxiLiteWriteSlaveType
mAxiClk	in	sl
mAxiClkRst	in	sl
mAxiReadMaster	out	AxiLiteReadMasterType
mAxiReadSlave	in	AxiLiteReadSlaveType
mAxiWriteMaster	out	AxiLiteWriteMasterType
mAxiWriteSlave	in	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteAsync.vhd
• build/SRC_VHDL/surf/AxiLiteAsync.vhd