Architecture >> AxiLiteAsync::STRUCTURE

Signals
s2mRst	sl
m2sRst	sl
readSlaveToMastDin	slv ( NUM_ADDR_BITS_G+ 2 downto 0 )
readSlaveToMastDout	slv ( NUM_ADDR_BITS_G+ 2 downto 0 )
readSlaveToMastFull	sl
readSlaveToMastValid	sl
readSlaveToMastRead	sl
readSlaveToMastWrite	sl
readMastToSlaveDin	slv ( 33 downto 0 )
readMastToSlaveDout	slv ( 33 downto 0 )
readMastToSlaveFull	sl
readMastToSlaveValid	sl
readMastToSlaveRead	sl
readMastToSlaveWrite	sl
writeAddrSlaveToMastDin	slv ( NUM_ADDR_BITS_G+ 2 downto 0 )
writeAddrSlaveToMastDout	slv ( NUM_ADDR_BITS_G+ 2 downto 0 )
writeAddrSlaveToMastFull	sl
writeAddrSlaveToMastValid	sl
writeAddrSlaveToMastRead	sl
writeAddrSlaveToMastWrite	sl
writeDataSlaveToMastDin	slv ( 35 downto 0 )
writeDataSlaveToMastDout	slv ( 35 downto 0 )
writeDataSlaveToMastFull	sl
writeDataSlaveToMastValid	sl
writeDataSlaveToMastRead	sl
writeDataSlaveToMastWrite	sl
writeMastToSlaveDin	slv ( 1 downto 0 )
writeMastToSlaveDout	slv ( 1 downto 0 )
writeMastToSlaveFull	sl
writeMastToSlaveValid	sl
writeMastToSlaveRead	sl
writeMastToSlaveWrite	sl

Instantiations
loc_s2m_rstsync	RstSync <Entity RstSync>
loc_m2s_rstsync	RstSync <Entity RstSync>
u_readslavetomastfifo	FifoAsync <Entity FifoAsync>
u_readmasttoslavefifo	FifoAsync <Entity FifoAsync>
u_writeaddrslavetomastfifo	FifoAsync <Entity FifoAsync>
u_writedataslavetomastfifo	FifoAsync <Entity FifoAsync>
u_writemasttoslavefifo	FifoAsync <Entity FifoAsync>
loc_s2m_rstsync	RstSync <Entity RstSync>
loc_m2s_rstsync	RstSync <Entity RstSync>
u_readslavetomastfifo	FifoAsync <Entity FifoAsync>
u_readmasttoslavefifo	FifoAsync <Entity FifoAsync>
u_writeaddrslavetomastfifo	FifoAsync <Entity FifoAsync>
u_writedataslavetomastfifo	FifoAsync <Entity FifoAsync>
u_writemasttoslavefifo	FifoAsync <Entity FifoAsync>

The documentation for this design unit was generated from the following files:

Processes

Signals