Architecture >> AxiLiteAsync::STRUCTURE

Processes
comb	( m2sRstActive , r , sArReady , sAwReady , sAxiClkRst , sAxiReadMaster , sAxiWriteMaster , sBValid , sRValid , sWReady )
seq	( sAxiClk , sAxiClkRst )
PROCESS_1	( readSlaveToMastDout )
PROCESS_2	( writeAddrSlaveToMastDout )

Constants
FIFO_ADDR_WIDTH_C	positive := 4
REG_INIT_C	RegType := ( errMode = > ' 0 ' , rPend = > ' 0 ' , awPend = > ' 0 ' , wPend = > ' 0 ' )

Signals
sRst	sl
m2sRst	sl
readSlaveToMastDin	slv ( NUM_ADDR_BITS_G+ 2 downto 0 )
readSlaveToMastDout	slv ( NUM_ADDR_BITS_G+ 2 downto 0 )
readSlaveToMastFull	sl
readSlaveToMastValid	sl
readSlaveToMastRead	sl
readSlaveToMastWrite	sl
readMastToSlaveDin	slv ( 33 downto 0 )
readMastToSlaveDout	slv ( 33 downto 0 )
readMastToSlaveFull	sl
readMastToSlaveValid	sl
readMastToSlaveRead	sl
readMastToSlaveWrite	sl
writeAddrSlaveToMastDin	slv ( NUM_ADDR_BITS_G+ 2 downto 0 )
writeAddrSlaveToMastDout	slv ( NUM_ADDR_BITS_G+ 2 downto 0 )
writeAddrSlaveToMastFull	sl
writeAddrSlaveToMastValid	sl
writeAddrSlaveToMastRead	sl
writeAddrSlaveToMastWrite	sl
writeDataSlaveToMastDin	slv ( 35 downto 0 )
writeDataSlaveToMastDout	slv ( 35 downto 0 )
writeDataSlaveToMastFull	sl
writeDataSlaveToMastValid	sl
writeDataSlaveToMastRead	sl
writeDataSlaveToMastWrite	sl
writeMastToSlaveDin	slv ( 1 downto 0 )
writeMastToSlaveDout	slv ( 1 downto 0 )
writeMastToSlaveFull	sl
writeMastToSlaveValid	sl
writeMastToSlaveRead	sl
writeMastToSlaveWrite	sl
m2sRstActive	sl
mAxiRstActive	sl
fifoRstReq	sl
fifoRst	sl
sArReady	sl
sRValid	sl
sAwReady	sl
sWReady	sl
sBValid	sl
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

Instantiations
loc_s_rstsync	RstSync <Entity RstSync>
loc_m2s_rstsync	RstSync <Entity RstSync>
u_fiforstreg	RegisterVector <Entity RegisterVector>
u_readslavetomastfifo	FifoAsync <Entity FifoAsync>
u_readmasttoslavefifo	FifoAsync <Entity FifoAsync>
u_writeaddrslavetomastfifo	FifoAsync <Entity FifoAsync>
u_writedataslavetomastfifo	FifoAsync <Entity FifoAsync>
u_writemasttoslavefifo	FifoAsync <Entity FifoAsync>

The documentation for this design unit was generated from the following file:

Processes

Constants