MmcmEmulation Entity Reference

Inheritance diagram for MmcmEmulation:

Collaboration diagram for MmcmEmulation:

Entities
MmcmEmulation.MmcmEmulation	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>

Generics
CLKIN_PERIOD_G	real := 10 . 0
DIVCLK_DIVIDE_G	integer range 1 to 106 := 2
CLKFBOUT_MULT_F_G	real range 1 . 0 to 128 . 0 := 20 . 0
CLKOUT0_DIVIDE_F_G	real range 1 . 0 to 128 . 0 := 1 . 0
CLKOUT1_DIVIDE_G	integer range 1 to 128 := 2
CLKOUT2_DIVIDE_G	integer range 1 to 128 := 3
CLKOUT3_DIVIDE_G	integer range 1 to 128 := 4
CLKOUT4_DIVIDE_G	integer range 1 to 128 := 5
CLKOUT5_DIVIDE_G	integer range 1 to 128 := 6
CLKOUT6_DIVIDE_G	integer range 1 to 128 := 7
CLKOUT0_PHASE_G	real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT1_PHASE_G	real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT2_PHASE_G	real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT3_PHASE_G	real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT4_PHASE_G	real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT5_PHASE_G	real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT6_PHASE_G	real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT0_DUTY_CYCLE_G	real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT1_DUTY_CYCLE_G	real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT2_DUTY_CYCLE_G	real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT3_DUTY_CYCLE_G	real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT4_DUTY_CYCLE_G	real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT5_DUTY_CYCLE_G	real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT6_DUTY_CYCLE_G	real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT0_RST_POLARITY_G	sl := ' 1 '
CLKOUT1_RST_POLARITY_G	sl := ' 1 '
CLKOUT2_RST_POLARITY_G	sl := ' 1 '
CLKOUT3_RST_POLARITY_G	sl := ' 1 '
CLKOUT4_RST_POLARITY_G	sl := ' 1 '
CLKOUT5_RST_POLARITY_G	sl := ' 1 '
CLKOUT6_RST_POLARITY_G	sl := ' 1 '

Ports
CLKIN	in	sl
RST	in	sl := ' 0 '
LOCKED	out	sl
CLKOUT0	out	sl
CLKOUT1	out	sl
CLKOUT2	out	sl
CLKOUT3	out	sl
CLKOUT4	out	sl
CLKOUT5	out	sl
CLKOUT6	out	sl

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The documentation for this design unit was generated from the following file:

• xilinx/general/tb/MmcmEmulation.vhd