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Constants | Instantiations | Signals
MmcmEmulation.MmcmEmulation Architecture Reference
Architecture >> MmcmEmulation::MmcmEmulation

Constants

VCO_PERIOD_REAL_C  real := ( real ( DIVCLK_DIVIDE_G ) * CLKIN_PERIOD_G ) / ( CLKFBOUT_MULT_F_G )
CLKOUT_PERIOD_REAL_C  RealArray := ( 0 = > ( VCO_PERIOD_REAL_C* CLKOUT0_DIVIDE_F_G ) , 1 = > ( VCO_PERIOD_REAL_C* CLKOUT1_DIVIDE_G ) , 2 = > ( VCO_PERIOD_REAL_C* CLKOUT2_DIVIDE_G ) , 3 = > ( VCO_PERIOD_REAL_C* CLKOUT3_DIVIDE_G ) , 4 = > ( VCO_PERIOD_REAL_C* CLKOUT4_DIVIDE_G ) , 5 = > ( VCO_PERIOD_REAL_C* CLKOUT5_DIVIDE_G ) , 6 = > ( VCO_PERIOD_REAL_C* CLKOUT6_DIVIDE_G ) )
CLKOUT_PERIOD_C  TimeArray := ( 0 = > ( CLKOUT_PERIOD_REAL_C ( 0 ) * ( 1 ns ) ) , 1 = > ( CLKOUT_PERIOD_REAL_C ( 1 ) * ( 1 ns ) ) , 2 = > ( CLKOUT_PERIOD_REAL_C ( 2 ) * ( 1 ns ) ) , 3 = > ( CLKOUT_PERIOD_REAL_C ( 3 ) * ( 1 ns ) ) , 4 = > ( CLKOUT_PERIOD_REAL_C ( 4 ) * ( 1 ns ) ) , 5 = > ( CLKOUT_PERIOD_REAL_C ( 5 ) * ( 1 ns ) ) , 6 = > ( CLKOUT_PERIOD_REAL_C ( 6 ) * ( 1 ns ) ) )
PHASE_OFFSET_C  TimeArray ( 6 downto 0 ) := ( others = > ( 1 ps ) )
CLK_HI_CYCLE_C  TimeArray := ( 0 = > ( CLKOUT_PERIOD_C ( 0 ) * CLKOUT0_DUTY_CYCLE_G ) , 1 = > ( CLKOUT_PERIOD_C ( 1 ) * CLKOUT1_DUTY_CYCLE_G ) , 2 = > ( CLKOUT_PERIOD_C ( 2 ) * CLKOUT2_DUTY_CYCLE_G ) , 3 = > ( CLKOUT_PERIOD_C ( 3 ) * CLKOUT3_DUTY_CYCLE_G ) , 4 = > ( CLKOUT_PERIOD_C ( 4 ) * CLKOUT4_DUTY_CYCLE_G ) , 5 = > ( CLKOUT_PERIOD_C ( 5 ) * CLKOUT5_DUTY_CYCLE_G ) , 6 = > ( CLKOUT_PERIOD_C ( 6 ) * CLKOUT6_DUTY_CYCLE_G ) )
CLK_LO_CYCLE_C  TimeArray := ( 0 = > ( CLKOUT_PERIOD_C ( 0 ) - CLK_HI_CYCLE_C ( 0 ) ) , 1 = > ( CLKOUT_PERIOD_C ( 1 ) - CLK_HI_CYCLE_C ( 1 ) ) , 2 = > ( CLKOUT_PERIOD_C ( 2 ) - CLK_HI_CYCLE_C ( 2 ) ) , 3 = > ( CLKOUT_PERIOD_C ( 3 ) - CLK_HI_CYCLE_C ( 3 ) ) , 4 = > ( CLKOUT_PERIOD_C ( 4 ) - CLK_HI_CYCLE_C ( 4 ) ) , 5 = > ( CLKOUT_PERIOD_C ( 5 ) - CLK_HI_CYCLE_C ( 5 ) ) , 6 = > ( CLKOUT_PERIOD_C ( 6 ) - CLK_HI_CYCLE_C ( 6 ) ) )
CLKOUT_RST_POLARITY_C  slv ( 6 downto 0 ) := ( CLKOUT6_RST_POLARITY_G& CLKOUT5_RST_POLARITY_G& CLKOUT4_RST_POLARITY_G& CLKOUT3_RST_POLARITY_G& CLKOUT2_RST_POLARITY_G& CLKOUT1_RST_POLARITY_G& CLKOUT0_RST_POLARITY_G )

Signals

phasedUp  slv ( 6 downto 0 ) := ( others = > ' 0 ' )
clkOut  slv ( 6 downto 0 ) := ( others = > ' 0 ' )

Instantiations

u_clkpgp  ClkRst <Entity ClkRst>
The documentation for this design unit was generated from the following file: