ClkRst Entity Reference

Inherited by AxiLiteAsyncTb, AxiLiteWriteFilterTb, AxiVersionTb, AxiStreamFlushTb, AxiStreamMuxTb, AxiStreamPipelineTb, AxiStreamPkgTb, AxiStreamResizeTb, AxiStreamRingBufferTb, AxiRamTb, AxiRingBufferTb, AxiLiteIpBusBridgeTb, AxiStreamDmaReadTb, SlvDelayRamTb, FifoFwftTb, FwftCntTb, GearboxTb, HeartbeatTb, SynchronizerFifoTb, SynchronizerOneShotTb, AxiLiteSaciMasterTb, AxiLiteSrpV0Tb, AxiStreamBytePackerTb, AxiStreamPacketizer2Tb, BoxcarFilterTb, BoxcarIntegratorTb, Code12b14bTb, DescrambleTb, DspAddSubTb, DspComparatorTb, Encoder12b14bTb, FirFilterSingleChannelTb, HammingEccTb, HtspCoreTb, I2cRegTb, Jesd204bTb, Pgp3Tb, Pgp4CoreLiteTb, Pgp4Tb, Pgp4TxLiteTb, RssiCoreTb, RssiInterleaveTb, Saci2ToAxiLiteTb, SaciAxiLiteMasterTb, SaciAxiLiteMasterTbWrapper, ScramblerTb, SrpV3AxiLiteTb, SrpV3AxiTb, SsiFifoTb, SsiFilterTb, SsiPrbsTb, SsiResizeFifoEofeTb, Ssp10b12bTb, Ssp12b14bTb, UartAxiLiteMasterTb, Ad9249Group, FirAverageTb, IirSimpleTb, EthMacFastTb, EthMacPauseTb, EthMacRxCsumFragTb, EthMacTb, IpV4EngineTb, RawEthFramerTb, UdpEngineTb, ClinkFramerTb, ClinkUartTb, CoaXPressCrcTb, GLinkGtx7FixedLatTb, HtspCaui4GtyTb, Pgp2bGtx7FixedLatWrapperTb, Pgp3Gtp7Tb, SaltCoreTb, SspLowSpeedDecoder8b10bWrapperTb, SugoiTopTb, DeviceDnaUltraScaleTb, and SelectioDeserUltraScaleTb.

Entities
ClkRst.ClkRst	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>

Generics
CLK_PERIOD_G	time := 10 ns
CLK_DELAY_G	time := 0 ns
RST_START_DELAY_G	time := 1 ns
RST_HOLD_TIME_G	time := 6 us
SYNC_RESET_G	boolean := false

Ports
hold	in	sl := ' 0 '
halt	in	sl := ' 0 '
clkP	out	sl := ' 0 '
clkN	out	sl := ' 1 '
rst	out	sl := ' 1 '
rstL	out	sl := ' 0 '

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The documentation for this design unit was generated from the following files:

• base/general/tb/ClkRst.vhd
• build/SRC_VHDL/surf/ClkRst.vhd