Pgp4CoreLiteTb Entity Reference

Inheritance diagram for Pgp4CoreLiteTb:

Collaboration diagram for Pgp4CoreLiteTb:

Entities
Pgp4CoreLiteTb.testbed	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
Pgp4Pkg	Package <Pgp4Pkg>

Ports
LINK_READY	out	std_logic
AXIS_ACLK	in	std_logic := ' 0 '
AXIS_ARESETN	in	std_logic := ' 0 '
S_AXIS_TVALID	in	std_logic := ' 0 '
S_AXIS_TDATA	in	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TSTRB	in	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TKEEP	in	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TLAST	in	std_logic := ' 0 '
S_AXIS_TDEST	in	std_logic_vector ( 0 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TID	in	std_logic_vector ( 0 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TUSER	in	std_logic_vector ( 0 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TREADY	out	std_logic
M_AXIS_TVALID	out	std_logic
M_AXIS_TDATA	out	std_logic_vector ( 63 downto 0 )
M_AXIS_TSTRB	out	std_logic_vector ( 7 downto 0 )
M_AXIS_TKEEP	out	std_logic_vector ( 7 downto 0 )
M_AXIS_TLAST	out	std_logic
M_AXIS_TDEST	out	std_logic_vector ( 0 downto 0 )
M_AXIS_TID	out	std_logic_vector ( 0 downto 0 )
M_AXIS_TUSER	out	std_logic_vector ( 0 downto 0 )
M_AXIS_TREADY	in	std_logic

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp4/core/tb/Pgp4CoreLiteTb.vhd