SURF
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HtspRxFifo Entity Reference
+ Inheritance diagram for HtspRxFifo:
+ Collaboration diagram for HtspRxFifo:

Entities

HtspRxFifo.mapping  architecture
 

Libraries

ieee 
surf 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
HtspPkg  Package <HtspPkg>

Generics

TPD_G  time := 1 ns
CASCADE_SIZE_G  positive := 1
FIFO_ADDR_WIDTH_G  positive := 12
FIFO_PAUSE_THRESH_G  positive := 256
INT_WIDTH_SELECT_G  string := " WIDE "
INT_DATA_WIDTH_G  positive := 64
TX_MAX_PAYLOAD_SIZE_G  positive := 8192
NUM_VC_G  positive

Ports

appClks   in   slv ( NUM_VC_G- 1 downto 0 )
appRsts   in   slv ( NUM_VC_G- 1 downto 0 )
appRxMasters   out   AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 )
appRxSlaves   in   AxiStreamSlaveArray ( NUM_VC_G- 1 downto 0 )
htspClk   in   sl
htspRst   in   sl
rxlinkReady   in   sl
htspRxMasters   in   AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 )
htspRxCtrl   out   AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 )

The documentation for this design unit was generated from the following file: