SrpV3AxiLite Entity Reference

Inheritance diagram for SrpV3AxiLite:

Collaboration diagram for SrpV3AxiLite:

Entities
SrpV3AxiLite.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>
AxiLitePkg	Package <AxiLitePkg>
math_real

Generics
TPD_G	time := 1 ns
INT_PIPE_STAGES_G	natural range 0 to 16 := 1
PIPE_STAGES_G	natural range 0 to 16 := 1
FIFO_PAUSE_THRESH_G	positive range 1 to 511 := 256
FIFO_SYNTH_MODE_G	string := " inferred "
FIFO_MEMORY_TYPE_G	string := " block "
FIFO_ADDR_WIDTH_G	integer range 9 to 48 := 9
TX_VALID_THOLD_G	positive range 1 to 511 := 500
TX_VALID_BURST_MODE_G	boolean := true
SLAVE_READY_EN_G	boolean := false
GEN_SYNC_FIFO_G	boolean := false
ENABLE_TIMER_G	boolean := true
AXIL_CLK_FREQ_G	real := 156 . 25E + 6
AXI_STREAM_CONFIG_G	AxiStreamConfigType

Ports
sAxisClk	in	sl
sAxisRst	in	sl
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
sAxisCtrl	out	AxiStreamCtrlType
mAxisClk	in	sl
mAxisRst	in	sl
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType
axilClk	in	sl
axilRst	in	sl
mAxilWriteMaster	out	AxiLiteWriteMasterType
mAxilWriteSlave	in	AxiLiteWriteSlaveType
mAxilReadMaster	out	AxiLiteReadMasterType
mAxilReadSlave	in	AxiLiteReadSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SrpV3AxiLite.vhd
• protocols/srp/rtl/SrpV3AxiLite.vhd