SrpV3AxiLite.rtl Architecture Reference

Architecture >> SrpV3AxiLite::rtl

Processes
comb	( axilRst , mAxilReadSlave , mAxilWriteSlave , r , rxCtrl , rxMaster , rxTLastTUser , txSlave )
seq	( axilClk )
comb	( axilRst , mAxilReadSlave , mAxilWriteSlave , r , rxCtrl , rxMaster , rxTLastTUser , txSlave )
seq	( axilClk )

Constants
AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 4 , TKEEP_COMP_C , TUSER_FIRST_LAST_C , 8 )
TIMEOUT_C	natural := ( getTimeRatio ( AXIL_CLK_FREQ_G , 10 . 0 ) - 1 )
SRP_VERSION_C	slv ( 7 downto 0 ) := x " 03 "
NON_POSTED_READ_C	slv ( 1 downto 0 ) := " 00 "
NON_POSTED_WRITE_C	slv ( 1 downto 0 ) := " 01 "
POSTED_WRITE_C	slv ( 1 downto 0 ) := " 10 "
NULL_C	slv ( 1 downto 0 ) := " 11 "
REG_INIT_C	RegType := ( timer = > 0 , hdrCnt = > ( others = > ' 0 ' ) , remVer = > ( others = > ' 0 ' ) , opCode = > ( others = > ' 0 ' ) , prot = > ( others = > ' 0 ' ) , timeoutSize = > ( others = > ' 0 ' ) , timeoutCnt = > ( others = > ' 0 ' ) , tid = > ( others = > ' 0 ' ) , tidDly = > ( others = > ' 1 ' ) , addr = > ( others = > ' 0 ' ) , reqSize = > ( others = > ' 0 ' ) , cnt = > ( others = > ' 0 ' ) , cntSize = > ( others = > ' 0 ' ) , memResp = > ( others = > ' 0 ' ) , timeout = > ' 0 ' , eofe = > ' 0 ' , frameError = > ' 0 ' , verMismatch = > ' 0 ' , reqSizeError = > ' 0 ' , ignoreMemResp = > ' 0 ' , rxRst = > ' 1 ' , overflowDet = > ' 0 ' , skip = > ' 0 ' , mAxilWriteMaster = > AXI_LITE_WRITE_MASTER_INIT_C , mAxilReadMaster = > AXI_LITE_READ_MASTER_INIT_C , rxSlave = > AXI_STREAM_SLAVE_INIT_C , txMaster = > AXI_STREAM_MASTER_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , HDR_REQ0_S , HDR_REQ1_S , HDR_REQ2_S , HDR_REQ3_S , HDR_RESP_S , FOOTER_S , AXIL_RD_REQ_S , AXIL_RD_RESP_S , AXIL_WR_REQ_S , AXIL_WR_RESP_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
axisMaster	AxiStreamMasterType
axisSlave	AxiStreamSlaveType
sCtrl	AxiStreamCtrlType
rxMaster	AxiStreamMasterType
rxSlave	AxiStreamSlaveType
rxCtrl	AxiStreamCtrlType
rxTLastTUser	slv ( 7 downto 0 )
txSlave	AxiStreamSlaveType
sAxisRxRst	sl
sRstTmp	sl
sRst	sl

Records
RegType

Instantiations
u_limiter	SsiFrameLimiter <Entity SsiFrameLimiter>
rx_fifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
sync_ctrl	SynchronizerVector <Entity SynchronizerVector>
sync_overflow	SynchronizerOneShot <Entity SynchronizerOneShot>
sync_rst	RstSync <Entity RstSync>
sync_rst_1	RstSync <Entity RstSync>
tx_fifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_limiter	SsiFrameLimiter <Entity SsiFrameLimiter>
rx_fifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
sync_ctrl	SynchronizerVector <Entity SynchronizerVector>
sync_overflow	SynchronizerOneShot <Entity SynchronizerOneShot>
sync_rst	RstSync <Entity RstSync>
sync_rst_1	RstSync <Entity RstSync>
tx_fifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>

---

The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SrpV3AxiLite.vhd
• protocols/srp/rtl/SrpV3AxiLite.vhd