DmaXvcWrapper Entity Reference

Inheritance diagram for DmaXvcWrapper:

Collaboration diagram for DmaXvcWrapper:

Entities
DmaXvcWrapper.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
EthMacPkg	Package <EthMacPkg>

Generics
TPD_G	time := 1 ns
COMMON_CLOCK_G	boolean := false
FIFO_ADDR_WIDTH_G	positive := 9
FIFO_SYNTH_MODE_G	string := " inferred "
FIFO_MEMORY_TYPE_G	string := " block "
DMA_AXIS_CONFIG_G	AxiStreamConfigType

Ports
xvcClk156	in	sl
xvcRst156	in	sl
dmaClk	in	sl
dmaRst	in	sl
dmaObMaster	in	AxiStreamMasterType
dmaObSlave	out	AxiStreamSlaveType
dmaIbMaster	out	AxiStreamMasterType
dmaIbSlave	in	AxiStreamSlaveType

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The documentation for this design unit was generated from the following file:

• xilinx/xvc-udp/rtl/DmaXvcWrapper.vhd