DmaXvcWrapper.rtl Architecture Reference

Architecture >> DmaXvcWrapper::rtl

Signals
ibXvcMaster	AxiStreamMasterType := axiStreamMasterInit ( EMAC_AXIS_CONFIG_C )
ibXvcSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
obXvcMaster	AxiStreamMasterType := axiStreamMasterInit ( EMAC_AXIS_CONFIG_C )
obXvcSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C

Instantiations
u_rx_fifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_xvc	UdpDebugBridgeWrapper <Entity UdpDebugBridgeWrapper>
u_tx_fifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>

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The documentation for this design unit was generated from the following file:

• xilinx/xvc-udp/rtl/DmaXvcWrapper.vhd