SsiSem Entity Reference

Inheritance diagram for SsiSem:

Collaboration diagram for SsiSem:

Entities
SsiSem.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
TextUtilPkg	Package <TextUtilPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>
SemPkg	Package <SemPkg>

Generics
TPD_G	time := 1 ns
COMMON_AXIL_CLK_G	boolean := false
COMMON_AXIS_CLK_G	boolean := false
SLAVE_AXI_CONFIG_G	AxiStreamConfigType
MASTER_AXI_CONFIG_G	AxiStreamConfigType

Ports
semClk	in	sl
semRst	in	sl
fpgaReload	in	sl := ' 0 '
fpgaReloadAddr	in	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
moduleIndex	in	slv ( 3 downto 0 ) := x " 0 "
axisClk	in	sl
axisRst	in	sl
semObAxisMaster	out	AxiStreamMasterType
semObAxisSlave	in	AxiStreamSlaveType
semIbAxisMaster	in	AxiStreamMasterType
semIbAxisSlave	out	AxiStreamSlaveType

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/sem/rtl/SsiSem.vhd