SsiSem.rtl Architecture Reference

Architecture >> SsiSem::rtl

Processes
comb	( axiReadMaster , axiWriteMaster , idx , r , rxAxisMaster , semOb , semRst , statusHalted , statusIdle , txAxisCtrl )
seq	( semClk )

Constants
SEM_AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 8 )
RET_CHAR_C	character := cr
RET_SLV_C	slv ( 7 downto 0 ) := conv_std_logic_vector ( character ' pos ( RET_CHAR_C ) , 8 )
REG_INIT_C	RegType := ( sofNext = > ' 1 ' , count = > ( others = > ' 0 ' ) , heartbeatCount = > ( others = > ' 0 ' ) , iprogIcapReqLast = > ' 0 ' , semIb = > SEM_IB_INIT_C , axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , txSsiMaster = > ssiMasterInit ( SEM_AXIS_CONFIG_C ) )

Signals
r	RegType := REG_INIT_C
rin	RegType
axiReadMaster	AxiLiteReadMasterType
axiReadSlave	AxiLiteReadSlaveType
axiWriteMaster	AxiLiteWriteMasterType
axiWriteSlave	AxiLiteWriteSlaveType
txAxisMaster	AxiStreamMasterType
txAxisCtrl	AxiStreamCtrlType
rxAxisMaster	AxiStreamMasterType
rxAxisSlave	AxiStreamSlaveType
statusIdle	sl
statusHalted	sl
semIb	SemIbType
semOb	SemObType
idx	slv ( 3 downto 0 )

Records
RegType

Instantiations
u_sem	SemWrapper <Entity SemWrapper>
u_syncfifo	SynchronizerFifo <Entity SynchronizerFifo>
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>
u_txfifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_rxfifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/sem/rtl/SsiSem.vhd