SrpV3Core Entity Reference

Inheritance diagram for SrpV3Core:

Collaboration diagram for SrpV3Core:

Entities
SrpV3Core.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>
AxiLitePkg	Package <AxiLitePkg>
SrpV3Pkg	Package <SrpV3Pkg>

Generics
TPD_G	time := 1 ns
PIPE_STAGES_G	natural range 0 to 16 := 1
SYNTH_MODE_G	string := " inferred "
FIFO_PAUSE_THRESH_G	positive range 1 to 511 := 256
TX_VALID_THOLD_G	positive := 1
SLAVE_READY_EN_G	boolean := false
GEN_SYNC_FIFO_G	boolean := false
SRP_CLK_FREQ_G	real := 156 . 25E + 6
AXI_STREAM_CONFIG_G	AxiStreamConfigType
UNALIGNED_ACCESS_G	boolean := false
BYTE_ACCESS_G	boolean := false
WRITE_EN_G	boolean := true
READ_EN_G	boolean := true

Ports
sAxisClk	in	sl
sAxisRst	in	sl
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
sAxisCtrl	out	AxiStreamCtrlType
mAxisClk	in	sl
mAxisRst	in	sl
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType
srpClk	in	sl
srpRst	in	sl
srpReq	out	SrpV3ReqType
srpAck	in	SrpV3AckType
srpWrMaster	out	AxiStreamMasterType
srpWrSlave	in	AxiStreamSlaveType
srpRdMaster	in	AxiStreamMasterType
srpRdSlave	out	AxiStreamSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SrpV3Core.vhd
• protocols/srp/rtl/SrpV3Core.vhd