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SrpV3Core.rtl Architecture Reference
Architecture >> SrpV3Core::rtl

Processes

comb  ( r , rxCtrl , rxMaster , srpAck , srpRdMasterInt , srpRst , srpWrSlaveInt , txSlave )
seq  ( srpClk )
comb  ( r , rxCtrl , rxMaster , srpAck , srpRdMasterInt , srpRst , srpWrSlaveInt , txSlave )
seq  ( srpClk )

Constants

TIMEOUT_C  natural := ( getTimeRatio ( SRP_CLK_FREQ_G , 10 . 0 ) - 1 )
SRP_AXIS_CONFIG_C  AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 4 , TDEST_BITS_C = > AXI_STREAM_CONFIG_G.TDEST_BITS_C , TID_BITS_C = > AXI_STREAM_CONFIG_G.TID_BITS_C , TKEEP_MODE_C = > TKEEP_COMP_C , TUSER_BITS_C = > 2 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
REG_INIT_C  RegType := ( timer = > 0 , hdrCnt = > ( others = > ' 0 ' ) , remVer = > ( others = > ' 0 ' ) , timeoutSize = > ( others = > ' 0 ' ) , timeoutCnt = > ( others = > ' 0 ' ) , txnCnt = > ( others = > ' 0 ' ) , memResp = > ( others = > ' 0 ' ) , timeout = > ' 0 ' , eofe = > ' 0 ' , frameError = > ' 0 ' , verMismatch = > ' 0 ' , reqError = > ' 0 ' , rxSlave = > AXI_STREAM_SLAVE_INIT_C , txMaster = > axiStreamMasterInit ( SRP_AXIS_CONFIG_C ) , state = > IDLE_S , srpReq = > SRPV3_REQ_INIT_C , srpWrMaster = > axiStreamMasterInit ( SRP_AXIS_CONFIG_C ) , srpRdSlave = > AXI_STREAM_SLAVE_INIT_C )

Types

StateType  ( IDLE_S , BLOWOFF_RX_S , BLOWOFF_READ_DATA_S , HDR_REQ_S , HDR_RESP_S , READ_S , WRITE_S , WAIT_ACK_S , FOOTER_S )

Signals

r  RegType := REG_INIT_C
rin  RegType
sCtrl  AxiStreamCtrlType
rxMaster  AxiStreamMasterType
rxSlave  AxiStreamSlaveType
rxCtrl  AxiStreamCtrlType
txSlave  AxiStreamSlaveType
srpRdMasterInt  AxiStreamMasterType
srpRdSlaveInt  AxiStreamSlaveType
srpWrMasterInt  AxiStreamMasterType
srpWrSlaveInt  AxiStreamSlaveType

Records

RegType 

Instantiations

rx_fifo  SsiFifo <Entity SsiFifo>
sync_ctrl  SynchronizerVector <Entity SynchronizerVector>
sync_overflow  SynchronizerOneShot <Entity SynchronizerOneShot>
tx_fifo  AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_rx  AxiStreamResize <Entity AxiStreamResize>
u_tx  AxiStreamResize <Entity AxiStreamResize>
rx_fifo  SsiFifo <Entity SsiFifo>
sync_ctrl  SynchronizerVector <Entity SynchronizerVector>
sync_overflow  SynchronizerOneShot <Entity SynchronizerOneShot>
tx_fifo  AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_rx  AxiStreamResize <Entity AxiStreamResize>
u_tx  AxiStreamResize <Entity AxiStreamResize>

The documentation for this design unit was generated from the following files: