Architecture >> SrpV3Core::rtl
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comb | ( r , rxCtrl , rxMaster , srpAck , srpRdMasterInt , srpRst , srpWrSlaveInt , txSlave ) |
seq | ( srpClk ) |
comb | ( r , rxCtrl , rxMaster , srpAck , srpRdMasterInt , srpRst , srpWrSlaveInt , txSlave ) |
seq | ( srpClk ) |
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TIMEOUT_C | natural := ( getTimeRatio ( SRP_CLK_FREQ_G , 10 . 0 ) - 1 ) |
SRP_AXIS_CONFIG_C | AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 4 , TDEST_BITS_C = > AXI_STREAM_CONFIG_G.TDEST_BITS_C , TID_BITS_C = > AXI_STREAM_CONFIG_G.TID_BITS_C , TKEEP_MODE_C = > TKEEP_COMP_C , TUSER_BITS_C = > 2 , TUSER_MODE_C = > TUSER_FIRST_LAST_C ) |
REG_INIT_C | RegType := ( timer = > 0 , hdrCnt = > ( others = > ' 0 ' ) , remVer = > ( others = > ' 0 ' ) , timeoutSize = > ( others = > ' 0 ' ) , timeoutCnt = > ( others = > ' 0 ' ) , txnCnt = > ( others = > ' 0 ' ) , memResp = > ( others = > ' 0 ' ) , timeout = > ' 0 ' , eofe = > ' 0 ' , frameError = > ' 0 ' , verMismatch = > ' 0 ' , reqError = > ' 0 ' , rxSlave = > AXI_STREAM_SLAVE_INIT_C , txMaster = > axiStreamMasterInit ( SRP_AXIS_CONFIG_C ) , state = > IDLE_S , srpReq = > SRPV3_REQ_INIT_C , srpWrMaster = > axiStreamMasterInit ( SRP_AXIS_CONFIG_C ) , srpRdSlave = > AXI_STREAM_SLAVE_INIT_C ) |
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StateType | ( IDLE_S , BLOWOFF_RX_S , BLOWOFF_READ_DATA_S , HDR_REQ_S , HDR_RESP_S , READ_S , WRITE_S , WAIT_ACK_S , FOOTER_S ) |
The documentation for this design unit was generated from the following files:
- build/SRC_VHDL/surf/SrpV3Core.vhd
- protocols/srp/rtl/SrpV3Core.vhd