SsiFifo Entity Reference

Inheritance diagram for SsiFifo:

Collaboration diagram for SsiFifo:

Entities
SsiFifo.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
INT_PIPE_STAGES_G	natural := 0
PIPE_STAGES_G	natural := 1
SLAVE_READY_EN_G	boolean := true
VALID_THOLD_G	natural := 1
VALID_BURST_MODE_G	boolean := false
GEN_SYNC_FIFO_G	boolean := false
FIFO_ADDR_WIDTH_G	positive := 9
FIFO_FIXED_THRESH_G	boolean := true
FIFO_PAUSE_THRESH_G	positive := 1
SYNTH_MODE_G	string := " inferred "
MEMORY_TYPE_G	string := " block "
INT_WIDTH_SELECT_G	string := " WIDE "
INT_DATA_WIDTH_G	positive := 16
LAST_FIFO_ADDR_WIDTH_G	natural := 0
CASCADE_PAUSE_SEL_G	natural := 0
CASCADE_SIZE_G	positive := 1
SLAVE_AXI_CONFIG_G	AxiStreamConfigType
MASTER_AXI_CONFIG_G	AxiStreamConfigType

Ports
sAxisClk	in	sl
sAxisRst	in	sl
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
sAxisCtrl	out	AxiStreamCtrlType
fifoPauseThresh	in	slv ( FIFO_ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 1 ' )
fifoWrCnt	out	slv ( FIFO_ADDR_WIDTH_G- 1 downto 0 )
sAxisDropWord	out	sl
sAxisDropFrame	out	sl
mAxisDropWord	out	sl
mAxisDropFrame	out	sl
lockupRstEvent	out	sl
mAxisClk	in	sl
mAxisRst	in	sl
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SsiFifo.vhd
• protocols/ssi/rtl/SsiFifo.vhd