Architecture >> SsiFifo::rtl
|
comb | ( fifoFull , r , sAxisRst , txMaster ) |
seq | ( sAxisClk , sAxisRst ) |
comb | ( fifoFull , r , sAxisRst , txMaster ) |
seq | ( sAxisClk , sAxisRst ) |
|
REG_INIT_C | RegType := ( fifoRst = > ' 0 ' , cnt = > x " 0 " , state = > WAIT_S ) |
|
r | RegType := REG_INIT_C |
rin | RegType |
rxMaster | AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C |
rxSlave | AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C |
rxCtrl | AxiStreamCtrlType := AXI_STREAM_CTRL_INIT_C |
txMaster | AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C |
txSlave | AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C |
txTLastTUser | slv ( 7 downto 0 ) := x " 00 " |
obAxisMaster | AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C |
obAxisSlave | AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C |
fifoFull | sl := ' 0 ' |
fifoRst | sl := ' 0 ' |
The documentation for this design unit was generated from the following files:
- build/SRC_VHDL/surf/SsiFifo.vhd
- protocols/ssi/rtl/SsiFifo.vhd