AxiRingBuffer Entity Reference

Inheritance diagram for AxiRingBuffer:

Collaboration diagram for AxiRingBuffer:

Entities
AxiRingBuffer.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiPkg	Package <AxiPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
SsiPkg	Package <SsiPkg>

Generics
TPD_G	time := 1 ns
ENABLE_DEFAULT_G	sl := ' 0 '
DATA_BYTES_G	positive := 8
RING_BUFF_ADDR_WIDTH_G	positive := 9
SYNTH_MODE_G	string := " inferred "
MEMORY_TYPE_G	string := " block "
AXIL_CLK_IS_DATA_CLK_G	boolean := false
AXI_CLK_IS_DATA_CLK_G	boolean := false
AXI_BASE_ADDR_G	slv ( 63 downto 0 ) := ( others = > ' 0 ' )
BURST_BYTES_G	positive range 1 to 4096 := 4096
AXIS_CLK_IS_DATA_CLK_G	boolean := false
AXIS_TDEST_G	slv ( 7 downto 0 ) := x " 00 "
AXIS_CONFIG_G	AxiStreamConfigType

Ports
dataClk	in	sl
dataRst	in	sl := ' 0 '
dataValid	in	sl := ' 1 '
dataValue	in	slv ( 8 * DATA_BYTES_G- 1 downto 0 )
extTrig	in	sl := ' 0 '
axiClk	in	sl
axiRst	in	sl
axiReady	in	sl := ' 1 '
mAxiWriteMaster	out	AxiWriteMasterType
mAxiWriteSlave	in	AxiWriteSlaveType
mAxiReadMaster	out	AxiReadMasterType
mAxiReadSlave	in	AxiReadSlaveType
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
axisClk	in	sl
axisRst	in	sl
axisMaster	out	AxiStreamMasterType
axisSlave	in	AxiStreamSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi4/rtl/AxiRingBuffer.vhd
• build/SRC_VHDL/surf/AxiRingBuffer.vhd