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Constants | Instantiations | Processes | Records | Signals | Subtypes | Types
AxiRingBuffer.rtl Architecture Reference
Architecture >> AxiRingBuffer::rtl

Processes

comb  ( axiRdy , axiReadSlave , axiWriteSlave , bramData , dataRst , dataValid , dataValue , extTrig , r , readMaster , txSlave , writeMaster )
seq  ( dataClk )
comb  ( axiRdy , axiReadSlave , axiWriteSlave , bramData , dataRst , dataValid , dataValue , extTrig , r , readMaster , txSlave , writeMaster )
seq  ( dataClk )

Constants

DATA_BITSIZE_C  positive := log2 ( DATA_BYTES_G )
BURST_BITSIZE_C  positive := log2 ( BURST_BYTES_G )
MEM_BITSIZE_C  positive := RING_BUFF_ADDR_WIDTH_G+ DATA_BITSIZE_C
AXI_CONFIG_C  AxiConfigType := ( ADDR_WIDTH_C = > 64 , DATA_BYTES_C = > DATA_BYTES_G , ID_BITS_C = > 1 , LEN_BITS_C = > 8 )
AXI_WR_MST_INIT_C  AxiWriteMasterType := ( awvalid = > ' 0 ' , awaddr = > AXI_BASE_ADDR_G , awid = > ( others = > ' 0 ' ) , awlen = > getAxiLen ( AXI_CONFIG_C , BURST_BYTES_G ) , awsize = > toSlv ( DATA_BITSIZE_C , 3 ) , awburst = > " 01 " , awlock = > ( others = > ' 0 ' ) , awprot = > ( others = > ' 0 ' ) , awcache = > " 0000 " , awqos = > ( others = > ' 0 ' ) , awregion = > ( others = > ' 0 ' ) , wdata = > ( others = > ' 0 ' ) , wlast = > ' 0 ' , wvalid = > ' 0 ' , wid = > ( others = > ' 0 ' ) , wstrb = > ( others = > ' 1 ' ) , bready = > ' 1 ' )
AXI_RD_MST_INIT_C  AxiReadMasterType := ( arvalid = > ' 0 ' , araddr = > AXI_BASE_ADDR_G , arid = > ( others = > ' 0 ' ) , arlen = > getAxiLen ( AXI_CONFIG_C , BURST_BYTES_G ) , arsize = > toSlv ( DATA_BITSIZE_C , 3 ) , arburst = > " 01 " , arlock = > ( others = > ' 0 ' ) , arprot = > ( others = > ' 0 ' ) , arcache = > " 0000 " , arqos = > ( others = > ' 0 ' ) , arregion = > ( others = > ' 0 ' ) , rready = > ' 0 ' )
AXIS_CONFIG_C  AxiStreamConfigType := ssiAxiStreamConfig ( dataBytes = > DATA_BYTES_G , tKeepMode = > TKEEP_FIXED_C , tUserMode = > TUSER_FIRST_LAST_C , tDestBits = > 8 , tUserBits = > 2 , tIdBits = > 0 )
REG_INIT_C  RegType := ( cntRst = > ' 0 ' , readoutCnt = > ( others = > ' 0 ' ) , dropTrigCnt = > ( others = > ' 0 ' ) , wrErrCnt = > ( others = > ' 0 ' ) , dataValid = > ' 0 ' , dataValue = > ( others = > ' 0 ' ) , extTrig = > ' 0 ' , softTrig = > ' 0 ' , continuousMode = > ' 0 ' , enableMode = > ENABLE_DEFAULT_G , bramWe = > ' 0 ' , bramWrCnt = > ( others = > ' 0 ' ) , bramAddr = > ( others = > ' 0 ' ) , bramWrDat = > ( others = > ' 0 ' ) , bramLat = > ( others = > ' 0 ' ) , ready = > ' 0 ' , armed = > ' 0 ' , memIdx = > ( others = > ' 0 ' ) , startIdx = > ( others = > ' 0 ' ) , rdWrdCnt = > ( others = > ' 0 ' ) , wrdOffset = > ( others = > ' 0 ' ) , axiWriteMaster = > AXI_WR_MST_INIT_C , axiReadMaster = > AXI_RD_MST_INIT_C , txMaster = > axiStreamMasterInit ( AXIS_CONFIG_C ) , readSlave = > AXI_LITE_READ_SLAVE_INIT_C , writeSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , state = > IDLE_S )

Types

StateType  ( IDLE_S , WR_AXI_S , WR_BRAM_S , RD_AXI_ADDR_S , RD_AXI_DATA_S , RD_BRAM_S )

Subtypes

AXI_BURST_RANGE_C  integer range BURST_BITSIZE_C- 1 downto 0
AXI_BUF_RANGE_C  integer range MEM_BITSIZE_C- 1 downto 0

Signals

r  RegType := REG_INIT_C
rin  RegType
axiWriteMaster  AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C
axiWriteSlave  AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C
axiReadMaster  AxiReadMasterType := AXI_READ_MASTER_INIT_C
axiReadSlave  AxiReadSlaveType := AXI_READ_SLAVE_INIT_C
readMaster  AxiLiteReadMasterType
writeMaster  AxiLiteWriteMasterType
axiRdy  sl
bramData  slv ( 8 * DATA_BYTES_G- 1 downto 0 )
txMaster  AxiStreamMasterType
txSlave  AxiStreamSlaveType

Records

RegType 

Instantiations

u_axiliteasync  AxiLiteAsync <Entity AxiLiteAsync>
u_axirdy  Synchronizer <Entity Synchronizer>
u_bram  SimpleDualPortRamXpm <Entity SimpleDualPortRamXpm>
u_bram  SimpleDualPortRam <Entity SimpleDualPortRam>
axi_rx_fifo  AxiReadPathFifo <Entity AxiReadPathFifo>
axi_tx_fifo  AxiWritePathFifo <Entity AxiWritePathFifo>
axis_tx_fifo  AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_axiliteasync  AxiLiteAsync <Entity AxiLiteAsync>
u_axirdy  Synchronizer <Entity Synchronizer>
u_bram  SimpleDualPortRamXpm <Entity SimpleDualPortRamXpm>
u_bram  SimpleDualPortRam <Entity SimpleDualPortRam>
axi_rx_fifo  AxiReadPathFifo <Entity AxiReadPathFifo>
axi_tx_fifo  AxiWritePathFifo <Entity AxiWritePathFifo>
axis_tx_fifo  AxiStreamFifoV2 <Entity AxiStreamFifoV2>
The documentation for this design unit was generated from the following files: