AxiWritePathFifo Entity Reference

Inheritance diagram for AxiWritePathFifo:

Collaboration diagram for AxiWritePathFifo:

Entities
AxiWritePathFifo.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiPkg	Package <AxiPkg>

Generics
TPD_G	time := 1 ns
GEN_SYNC_FIFO_G	boolean := false
ADDR_LSB_G	natural range 0 to 63 := 0
ID_FIXED_EN_G	boolean := false
SIZE_FIXED_EN_G	boolean := false
BURST_FIXED_EN_G	boolean := false
LEN_FIXED_EN_G	boolean := false
LOCK_FIXED_EN_G	boolean := false
PROT_FIXED_EN_G	boolean := false
CACHE_FIXED_EN_G	boolean := false
ADDR_MEMORY_TYPE_G	string := " block "
ADDR_CASCADE_SIZE_G	integer range 1 to ( 2 ** 24 ) := 1
ADDR_FIFO_ADDR_WIDTH_G	integer range 4 to 48 := 9
DATA_MEMORY_TYPE_G	string := " block "
DATA_CASCADE_SIZE_G	integer range 1 to ( 2 ** 24 ) := 1
DATA_FIFO_ADDR_WIDTH_G	integer range 4 to 48 := 9
DATA_FIFO_PAUSE_THRESH_G	integer range 1 to ( 2 ** 24 ) := 500
RESP_MEMORY_TYPE_G	string := " block "
RESP_CASCADE_SIZE_G	integer range 1 to ( 2 ** 24 ) := 1
RESP_FIFO_ADDR_WIDTH_G	integer range 4 to 48 := 9
AXI_CONFIG_G	AxiConfigType

Ports
sAxiClk	in	sl
sAxiRst	in	sl
sAxiWriteMaster	in	AxiWriteMasterType
sAxiWriteSlave	out	AxiWriteSlaveType
sAxiCtrl	out	AxiCtrlType
mAxiClk	in	sl
mAxiRst	in	sl
mAxiWriteMaster	out	AxiWriteMasterType
mAxiWriteSlave	in	AxiWriteSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi4/rtl/AxiWritePathFifo.vhd
• build/SRC_VHDL/surf/AxiWritePathFifo.vhd