AxiWritePathFifo.rtl Architecture Reference

Architecture >> AxiWritePathFifo::rtl

Functions
slv	addrToSlv ( din: in AxiWriteMasterType )
slv	dataToSlv ( din: in AxiWriteMasterType )
slv	respToSlv ( din: in AxiWriteSlaveType )
slv	addrToSlv ( din: in AxiWriteMasterType )
slv	dataToSlv ( din: in AxiWriteMasterType )
slv	respToSlv ( din: in AxiWriteSlaveType )

Processes
PROCESS_15	( addrFifoAFull , addrFifoDout , addrFifoValid , dataFifoAFull , dataFifoDout , dataFifoValid , respFifoAFull , respFifoDout , respFifoValid , sAxiWriteMaster )
PROCESS_98	( addrFifoAFull , addrFifoDout , addrFifoValid , dataFifoAFull , dataFifoDout , dataFifoValid , respFifoAFull , respFifoDout , respFifoValid , sAxiWriteMaster )

Procedures
	slvToAddr( din: in slv ( ADDR_FIFO_SIZE_C- 1 downto 0 ) valid: in sl slave: in AxiWriteMasterType master: inout AxiWriteMasterType )
	slvToData( din: in slv ( DATA_FIFO_SIZE_C- 1 downto 0 ) valid: in sl slave: in AxiWriteMasterType master: inout AxiWriteMasterType )
	slvToResp( din: in slv ( RESP_FIFO_SIZE_C- 1 downto 0 ) valid: in sl master: in AxiWriteMasterType slave: inout AxiWriteSlaveType )
	slvToAddr( din: in slv ( ADDR_FIFO_SIZE_C- 1 downto 0 ) valid: in sl slave: in AxiWriteMasterType master: inout AxiWriteMasterType )
	slvToData( din: in slv ( DATA_FIFO_SIZE_C- 1 downto 0 ) valid: in sl slave: in AxiWriteMasterType master: inout AxiWriteMasterType )
	slvToResp( din: in slv ( RESP_FIFO_SIZE_C- 1 downto 0 ) valid: in sl master: in AxiWriteMasterType slave: inout AxiWriteSlaveType )

Constants
ADDR_BITS_C	integer := AXI_CONFIG_G.ADDR_WIDTH_C- ADDR_LSB_G
ID_BITS_C	integer := ite ( ID_FIXED_EN_G , 0 , AXI_CONFIG_G.ID_BITS_C )
LEN_BITS_C	integer := ite ( LEN_FIXED_EN_G , 0 , AXI_CONFIG_G.LEN_BITS_C )
SIZE_BITS_C	integer := ite ( SIZE_FIXED_EN_G , 0 , 3 )
BURST_BITS_C	integer := ite ( BURST_FIXED_EN_G , 0 , 2 )
LOCK_BITS_C	integer := ite ( LOCK_FIXED_EN_G , 0 , 2 )
PROT_BITS_C	integer := ite ( PROT_FIXED_EN_G , 0 , 3 )
CACHE_BITS_C	integer := ite ( CACHE_FIXED_EN_G , 0 , 4 )
DATA_BITS_C	integer := AXI_CONFIG_G.DATA_BYTES_C* 8
STRB_BITS_C	integer := AXI_CONFIG_G.DATA_BYTES_C
RESP_BITS_C	integer := 2
ADDR_FIFO_SIZE_C	integer := ADDR_BITS_C+ ID_BITS_C+ LEN_BITS_C+ SIZE_BITS_C+ BURST_BITS_C+ LOCK_BITS_C+ PROT_BITS_C+ CACHE_BITS_C
DATA_FIFO_SIZE_C	integer := 1 + DATA_BITS_C+ STRB_BITS_C+ ID_BITS_C
RESP_FIFO_SIZE_C	integer := RESP_BITS_C+ ID_BITS_C

Signals
addrFifoWrite	sl
addrFifoDin	slv ( ADDR_FIFO_SIZE_C- 1 downto 0 )
addrFifoDout	slv ( ADDR_FIFO_SIZE_C- 1 downto 0 )
addrFifoValid	sl
addrFifoAFull	sl
addrFifoRead	sl
dataFifoWrite	sl
dataFifoDin	slv ( DATA_FIFO_SIZE_C- 1 downto 0 )
dataFifoDout	slv ( DATA_FIFO_SIZE_C- 1 downto 0 )
dataFifoValid	sl
dataFifoAFull	sl
dataFifoRead	sl
respFifoWrite	sl
respFifoDin	slv ( RESP_FIFO_SIZE_C- 1 downto 0 )
respFifoDout	slv ( RESP_FIFO_SIZE_C- 1 downto 0 )
respFifoValid	sl
respFifoAFull	sl
respFifoRead	sl

Instantiations
u_addrfifo	FifoCascade <Entity FifoCascade>
u_datafifo	FifoCascade <Entity FifoCascade>
u_respfifo	FifoCascade <Entity FifoCascade>
u_addrfifo	FifoCascade <Entity FifoCascade>
u_datafifo	FifoCascade <Entity FifoCascade>
u_respfifo	FifoCascade <Entity FifoCascade>

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The documentation for this design unit was generated from the following files:

• axi/axi4/rtl/AxiWritePathFifo.vhd
• build/SRC_VHDL/surf/AxiWritePathFifo.vhd