PgpRxVcFifo Entity Reference

Inheritance diagram for PgpRxVcFifo:

Collaboration diagram for PgpRxVcFifo:

Entities
PgpRxVcFifo.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
ROGUE_SIM_EN_G	boolean := false
INT_PIPE_STAGES_G	natural := 0
PIPE_STAGES_G	natural := 1
VALID_THOLD_G	natural := 1
VALID_BURST_MODE_G	boolean := false
SYNTH_MODE_G	string := " inferred "
MEMORY_TYPE_G	string := " block "
GEN_SYNC_FIFO_G	boolean := false
FIFO_ADDR_WIDTH_G	positive := 9
FIFO_PAUSE_THRESH_G	positive := 256
PHY_AXI_CONFIG_G	AxiStreamConfigType
APP_AXI_CONFIG_G	AxiStreamConfigType

Ports
pgpClk	in	sl
pgpRst	in	sl
rxlinkReady	in	sl
pgpRxMaster	in	AxiStreamMasterType
pgpRxCtrl	out	AxiStreamCtrlType
pgpRxSlave	out	AxiStreamSlaveType
axisClk	in	sl
axisRst	in	sl
axisMaster	out	AxiStreamMasterType
axisSlave	in	AxiStreamSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/PgpRxVcFifo.vhd
• protocols/pgp/shared/PgpRxVcFifo.vhd