Pgp4RxProtocol Entity Reference

Inheritance diagram for Pgp4RxProtocol:

Collaboration diagram for Pgp4RxProtocol:

Entities
Pgp4RxProtocol.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiStreamPacketizer2Pkg	Package <AxiStreamPacketizer2Pkg>
SsiPkg	Package <SsiPkg>
Pgp4Pkg	Package <Pgp4Pkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
RX_CRC_PIPELINE_G	natural range 0 to 1 := 0
NUM_VC_G	integer range 1 to 16 := 4

Ports
pgpRxClk	in	sl
pgpRxRst	in	sl
pgpRxIn	in	Pgp4RxInType := PGP4_RX_IN_INIT_C
pgpRxOut	out	Pgp4RxOutType
pgpRxMaster	out	AxiStreamMasterType
pgpRxSlave	in	AxiStreamSlaveType
remRxFifoCtrl	out	AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 )
remRxLinkReady	out	sl
locRxLinkReady	out	sl
linkError	in	sl
phyRxActive	in	sl
protRxValid	in	sl
protRxPhyInit	out	sl
protRxData	in	slv ( 63 downto 0 )
protRxHeader	in	slv ( 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Pgp4RxProtocol.vhd
• protocols/pgp/pgp4/core/rtl/Pgp4RxProtocol.vhd