AxiStreamRingBuffer Entity Reference

Inheritance diagram for AxiStreamRingBuffer:

Collaboration diagram for AxiStreamRingBuffer:

Entities
AxiStreamRingBuffer.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
SsiPkg	Package <SsiPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
SYNTH_MODE_G	string := " inferred "
MEMORY_TYPE_G	string := " block "
COMMON_CLK_G	boolean := false
DATA_BYTES_G	positive := 16
RAM_ADDR_WIDTH_G	positive := 9
INT_PIPE_STAGES_G	natural := 1
PIPE_STAGES_G	natural := 1
GEN_SYNC_FIFO_G	boolean := false
FIFO_MEMORY_TYPE_G	string := " block "
FIFO_ADDR_WIDTH_G	positive := 9
AXI_STREAM_CONFIG_G	AxiStreamConfigType

Ports
dataClk	in	sl
dataRst	in	sl := ' 0 '
dataValid	in	sl := ' 1 '
dataValue	in	slv ( 8 * DATA_BYTES_G- 1 downto 0 )
extTrig	in	sl := ' 0 '
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
axisClk	in	sl
axisRst	in	sl
axisMaster	out	AxiStreamMasterType
axisSlave	in	AxiStreamSlaveType

---

The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamRingBuffer.vhd
• build/SRC_VHDL/surf/AxiStreamRingBuffer.vhd