AxiStreamRingBuffer.rtl Architecture Reference

Architecture >> AxiStreamRingBuffer::rtl

Processes
dataComb	( axilRstSync , bufferClearSync , dataR , dataRst , dataValid , dataValue , extTrig , softTrigSync )
dataSeq	( dataClk , dataRst )
axiComb	( armed , axilR , axilReadMaster , axilRst , axilWriteMaster , bufferLength , dataRstSync , firstAddr , ramRdData , readReq , txSlave )
axiSeq	( axilClk , axilRst )
dataComb	( axilRstSync , bufferClearSync , dataR , dataRst , dataValid , dataValue , extTrig , softTrigSync )
dataSeq	( dataClk , dataRst )
axiComb	( armed , axilR , axilReadMaster , axilRst , axilWriteMaster , bufferLength , dataRstSync , firstAddr , ramRdData , readReq , txSlave )
axiSeq	( axilClk , axilRst )

Constants
AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( dataBytes = > DATA_BYTES_G , tKeepMode = > TKEEP_FIXED_C , tUserMode = > TUSER_FIRST_LAST_C , tDestBits = > 0 , tUserBits = > 2 , tIdBits = > 0 )
DATA_REG_INIT_C	DataRegType := ( enable = > ' 1 ' , armed = > ' 0 ' , ramWrEn = > ' 0 ' , readReq = > ' 0 ' , ramWrData = > ( others = > ' 0 ' ) , bufferLength = > ( others = > ' 0 ' ) , firstAddr = > ( others = > ' 0 ' ) , nextAddr = > ( others = > ' 0 ' ) )
AXIL_REG_INIT_C	AxilRegType := ( trigCnt = > ( others = > ' 0 ' ) , continuous = > ' 0 ' , softTrig = > ' 0 ' , bufferClear = > ' 0 ' , wordCnt = > ( others = > ' 0 ' ) , ramRdAddr = > ( others = > ' 0 ' ) , rdEn = > " 000 " , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , txMaster = > axiStreamMasterInit ( AXIS_CONFIG_C ) , dataState = > IDLE_S , dataStateIdx = > ( others = > ' 0 ' ) , trigState = > IDLE_S , trigStateIdx = > ( others = > ' 0 ' ) )

Types
DataStateType	( IDLE_S , MOVE_S , CLEARED_S )
TrigStateType	( IDLE_S , ARMED_S , WAIT_S )

Signals
dataR	DataRegType := DATA_REG_INIT_C
dataRin	DataRegType
softTrigSync	sl
bufferClearSync	sl
axilR	AxilRegType := AXIL_REG_INIT_C
axilRin	AxilRegType
fifoDin	slv ( 2 * RAM_ADDR_WIDTH_G- 1 downto 0 )
fifoDout	slv ( 2 * RAM_ADDR_WIDTH_G- 1 downto 0 )
ramRdData	slv ( 8 * DATA_BYTES_G- 1 downto 0 )
firstAddr	slv ( RAM_ADDR_WIDTH_G- 1 downto 0 )
bufferLength	slv ( RAM_ADDR_WIDTH_G- 1 downto 0 )
readReq	sl
armed	sl
fifoRst	sl
axilRstSync	sl
dataRstSync	sl
txSlave	AxiStreamSlaveType

Records
DataRegType
AxilRegType

Instantiations
u_ram	SimpleDualPortRamXpm <Entity SimpleDualPortRamXpm>
u_ram	SimpleDualPortRamAlteraMf <Entity SimpleDualPortRamAlteraMf>
u_ram	SimpleDualPortRam <Entity SimpleDualPortRam>
u_syncvec_dataclk	SynchronizerVector <Entity SynchronizerVector>
u_rstsync_axilrst	RstSync <Entity RstSync>
u_sync_readreq	SynchronizerFifo <Entity SynchronizerFifo>
u_syncvec_axilclk	SynchronizerVector <Entity SynchronizerVector>
u_rstsync_datarst	RstSync <Entity RstSync>
tx_fifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_ram	SimpleDualPortRamXpm <Entity SimpleDualPortRamXpm>
u_ram	SimpleDualPortRamAlteraMf <Entity SimpleDualPortRamAlteraMf>
u_ram	SimpleDualPortRam <Entity SimpleDualPortRam>
u_syncvec_dataclk	SynchronizerVector <Entity SynchronizerVector>
u_rstsync_axilrst	RstSync <Entity RstSync>
u_sync_readreq	SynchronizerFifo <Entity SynchronizerFifo>
u_syncvec_axilclk	SynchronizerVector <Entity SynchronizerVector>
u_rstsync_datarst	RstSync <Entity RstSync>
tx_fifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>

---

The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamRingBuffer.vhd
• build/SRC_VHDL/surf/AxiStreamRingBuffer.vhd