TenGigEthRst Entity Reference

Inheritance diagram for TenGigEthRst:

Collaboration diagram for TenGigEthRst:

Entities
TenGigEthRst.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns

Ports
extRst	in	sl
gtPowerGood	in	sl := ' 1 '
phyClk	in	sl
phyRst	in	sl
txClk322	in	sl
txUsrClk	out	sl
txUsrClk2	out	sl
gtTxRst	out	sl
gtRxRst	out	sl
txUsrRdy	out	sl
rstCntDone	out	sl
qplllock	in	sl
qpllRst	out	sl

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The documentation for this design unit was generated from the following file:

• ethernet/TenGigEthCore/core/rtl/TenGigEthRst.vhd