TenGigEthRst.rtl Architecture Reference

Architecture >> TenGigEthRst::rtl

Processes
PROCESS_226	( phyClk )
PROCESS_227	( txClock )

Signals
txClock	sl
txReset	sl
txReady	sl
rstCnt	slv ( 8 downto 0 ) := " 000000000 "
rstPulse	slv ( 3 downto 0 ) := " 1110 "

Instantiations
clk312_bufg	bufg
synchronizer_1	Synchronizer <Entity Synchronizer>
synchronizer_2	Synchronizer <Entity Synchronizer>

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The documentation for this design unit was generated from the following file:

• ethernet/TenGigEthCore/core/rtl/TenGigEthRst.vhd