Jesd204bTx Entity Reference

Inheritance diagram for Jesd204bTx:

Collaboration diagram for Jesd204bTx:

Entities
Jesd204bTx.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
Jesd204bPkg	Package <Jesd204bPkg>

Generics
TPD_G	time := 1 ns
INPUT_REG_G	boolean := false
OUTPUT_REG_G	boolean := false
F_G	positive := 2
K_G	positive := 32
L_G	positive range 1 to 32 := 2

Ports
axiClk	in	sl
axiRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
devClk_i	in	sl
devRst_i	in	sl
sysRef_i	in	sl
nSync_i	in	slv ( L_G- 1 downto 0 )
extSampleDataArray_i	in	sampleDataArray ( L_G- 1 downto 0 )
dacReady_o	out	slv ( L_G- 1 downto 0 )
gtTxReset_o	out	slv ( L_G- 1 downto 0 )
gtTxReady_i	in	slv ( L_G- 1 downto 0 )
r_jesdGtTxArr	out	jesdGtTxLaneTypeArray ( L_G- 1 downto 0 )
txDiffCtrl	out	Slv8Array ( L_G- 1 downto 0 )
txPostCursor	out	Slv8Array ( L_G- 1 downto 0 )
txPreCursor	out	Slv8Array ( L_G- 1 downto 0 )
txPowerDown	out	slv ( L_G- 1 downto 0 )
txPolarity	out	slv ( L_G- 1 downto 0 )
loopback	out	slv ( L_G- 1 downto 0 )
txEnable	out	slv ( L_G- 1 downto 0 )
txEnableL	out	slv ( L_G- 1 downto 0 )
pulse_o	out	slv ( L_G- 1 downto 0 )
leds_o	out	slv ( 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Jesd204bTx.vhd
• protocols/jesd204b/rtl/Jesd204bTx.vhd