Architecture >> Jesd204bTx::rtl

Signals
s_lmfc	slv ( L_G- 1 downto 0 )
s_sysrefDlyTx	slv ( SYSRF_DLY_WIDTH_C- 1 downto 0 )
s_enableTx	slv ( L_G- 1 downto 0 )
s_replEnable	sl
s_scrEnable	sl
s_statusTxArr	txStatuRegisterArray ( L_G- 1 downto 0 )
s_dataValid	slv ( L_G- 1 downto 0 )
s_invertData	slv ( L_G- 1 downto 0 )
s_subClass	sl
s_gtReset	sl
s_clearErr	sl
s_sigTypeArr	Slv2Array ( L_G- 1 downto 0 )
s_rampStep	slv ( PER_STEP_WIDTH_C- 1 downto 0 )
s_squarePeriod	slv ( PER_STEP_WIDTH_C- 1 downto 0 )
s_posAmplitude	*slv ( F_G 8 - 1 downto 0 )**
s_negAmplitude	*slv ( F_G 8 - 1 downto 0 )**
s_testDataArr	sampleDataArray ( L_G- 1 downto 0 )
s_extDataArraySwap	sampleDataArray ( L_G- 1 downto 0 )
s_regSampleDataIn	sampleDataArray ( L_G- 1 downto 0 )
s_regSampleDataOut	sampleDataArray ( L_G- 1 downto 0 )
s_sampleDataArr	sampleDataArray ( L_G- 1 downto 0 )
s_sysrefSync	sl
s_sysrefRe	slv ( L_G- 1 downto 0 )
s_sysrefD	sl
s_nSync	slv ( L_G- 1 downto 0 )
s_invertSync	sl
s_nSyncSync	slv ( L_G- 1 downto 0 )
s_muxOutSelArr	Slv3Array ( L_G- 1 downto 0 )
s_jesdGtTxArr	jesdGtTxLaneTypeArray ( L_G- 1 downto 0 )

Instantiations
u_reg	JesdTxReg <Entity JesdTxReg>
u_teststream	JesdTestStreamTx <Entity JesdTestStreamTx>
synchronizer_sysref_inst	Synchronizer <Entity Synchronizer>
synchronizer_nsync_inst	SynchronizerVector <Entity SynchronizerVector>
u_sysrefdly	SlvDelay <Entity SlvDelay>
u_lmfcgen	JesdLmfcGen <Entity JesdLmfcGen>
u_jesdtxlane	JesdTxLane <Entity JesdTxLane>
u_reg	JesdTxReg <Entity JesdTxReg>
u_teststream	JesdTestStreamTx <Entity JesdTestStreamTx>
synchronizer_sysref_inst	Synchronizer <Entity Synchronizer>
synchronizer_nsync_inst	SynchronizerVector <Entity SynchronizerVector>
u_sysrefdly	SlvDelay <Entity SlvDelay>
u_lmfcgen	JesdLmfcGen <Entity JesdLmfcGen>
u_jesdtxlane	JesdTxLane <Entity JesdTxLane>

The documentation for this design unit was generated from the following files:

Processes

Signals