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JesdLmfcGen Entity Reference
Inheritance diagram for JesdLmfcGen:Entities | |
| JesdLmfcGen.rtl | architecture |
Libraries | |
| ieee | |
| surf | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_unsigned | |
| std_logic_arith | |
| StdRtlPkg | Package <StdRtlPkg> |
| Jesd204bpkg | |
Generics | |
| TPD_G | time := 1 ns |
| K_G | positive := 32 |
| F_G | positive := 2 |
Ports | ||
| clk | in | sl |
| rst | in | sl |
| nSync_i | in | sl |
| sysref_i | in | sl |
| sysrefRe_o | out | sl |
| lmfc_o | out | sl |
The documentation for this design unit was generated from the following files:
- build/SRC_VHDL/surf/JesdLmfcGen.vhd
- protocols/jesd204b/rtl/JesdLmfcGen.vhd
