JesdTxReg Entity Reference

Inheritance diagram for JesdTxReg:

Collaboration diagram for JesdTxReg:

Entities
JesdTxReg.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
Jesd204bPkg	Package <Jesd204bPkg>

Generics
TPD_G	time := 1 ns
L_G	positive range 1 to 16 := 2
F_G	positive := 2

Ports
axiClk_i	in	sl
axiRst_i	in	sl
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType
devClk_i	in	sl
devRst_i	in	sl
sysrefRe_i	in	sl
statusTxArr_i	in	txStatuRegisterArray ( L_G- 1 downto 0 )
muxOutSelArr_o	out	Slv3Array ( L_G- 1 downto 0 )
sigTypeArr_o	out	Slv2Array ( L_G- 1 downto 0 )
sysrefDlyTx_o	out	slv ( SYSRF_DLY_WIDTH_C- 1 downto 0 )
enableTx_o	out	slv ( L_G- 1 downto 0 )
replEnable_o	out	sl
scrEnable_o	out	sl
invertData_o	out	slv ( L_G- 1 downto 0 )
rampStep_o	out	slv ( PER_STEP_WIDTH_C- 1 downto 0 )
squarePeriod_o	out	slv ( PER_STEP_WIDTH_C- 1 downto 0 )
subClass_o	out	sl
gtReset_o	out	sl
clearErr_o	out	sl
invertSync_o	out	sl
posAmplitude_o	out	slv ( F_G* 8 - 1 downto 0 )
negAmplitude_o	out	slv ( F_G* 8 - 1 downto 0 )
txDiffCtrl	out	Slv8Array ( L_G- 1 downto 0 )
txPostCursor	out	Slv8Array ( L_G- 1 downto 0 )
txPreCursor	out	Slv8Array ( L_G- 1 downto 0 )
txPowerDown	out	slv ( L_G- 1 downto 0 )
txPolarity	out	slv ( L_G- 1 downto 0 )
loopback	out	slv ( L_G- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/JesdTxReg.vhd
• protocols/jesd204b/rtl/JesdTxReg.vhd