SlvDelay Entity Reference

Inheritance diagram for SlvDelay:

Entities
SlvDelay.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
SRL_EN_G	boolean := false
DELAY_G	natural := 1
REG_OUTPUT_G	boolean := false
WIDTH_G	positive := 1
INIT_G	slv := " 0 "

Ports
clk	in	sl
rst	in	sl := not RST_POLARITY_G
en	in	sl := ' 1 '
delay	in	slv ( log2 ( DELAY_G ) - 1 downto 0 ) := toSlv ( DELAY_G- 1 , log2 ( DELAY_G ) )
din	in	slv ( WIDTH_G- 1 downto 0 )
dout	out	slv ( WIDTH_G- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• base/delay/rtl/SlvDelay.vhd
• build/SRC_VHDL/surf/SlvDelay.vhd