SlvDelay.rtl Architecture Reference

Architecture >> SlvDelay::rtl

Processes
comb	( din , en , iDelay , r , rst )
seq	( clk )
REG	( clk )
comb	( din , en , iDelay , r , rst )
seq	( clk )
REG	( clk )

Constants
INIT_C	slv ( WIDTH_G- 1 downto 0 ) := ite ( INIT_G = " 0 " , slvZero ( WIDTH_G ) , INIT_G )
REG_INIT_C	RegType := ( shift = > ( others = > INIT_C ) )
SRL_C	string := ite ( SRL_EN_G , " YES " , " NO " )

Types
VectorArray	( DELAY_G- 1 downto 0 ) slv ( WIDTH_G- 1 downto 0 )

Signals
r	RegType := REG_INIT_C
rin	RegType
iDelay	natural
iDout	slv ( WIDTH_G- 1 downto 0 )

Attributes
shreg_extract	string
shreg_extract	signal is SRL_C

Records
RegType

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The documentation for this design unit was generated from the following files:

• base/delay/rtl/SlvDelay.vhd
• build/SRC_VHDL/surf/SlvDelay.vhd