JesdTestStreamTx Entity Reference

Inheritance diagram for JesdTestStreamTx:

Entities
JesdTestStreamTx.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
Jesd204bpkg

Generics
TPD_G	time := 1 ns
F_G	positive := 2

Ports
clk	in	sl
rst	in	sl
enable_i	in	sl
type_i	in	slv ( 1 downto 0 )
rampStep_i	in	slv ( PER_STEP_WIDTH_C- 1 downto 0 )
squarePeriod_i	in	slv ( PER_STEP_WIDTH_C- 1 downto 0 )
posAmplitude_i	in	slv ( F_G* 8 - 1 downto 0 )
negAmplitude_i	in	slv ( F_G* 8 - 1 downto 0 )
sampleData_o	out	slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
pulse_o	out	sl

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/JesdTestStreamTx.vhd
• protocols/jesd204b/rtl/JesdTestStreamTx.vhd