JesdTestStreamTx.rtl Architecture Reference

Architecture >> JesdTestStreamTx::rtl

Processes
comb	( enable_i , negAmplitude_i , posAmplitude_i , r , rampStep_i , rst , squarePeriod_i , type_i )
seq	( clk )
comb	( enable_i , negAmplitude_i , posAmplitude_i , r , rampStep_i , rst , squarePeriod_i , type_i )
seq	( clk )

Constants
SAM_IN_WORD_C	positive := ( GT_WORD_SIZE_C/ F_G )
REG_INIT_C	RegType := ( typeDly = > ( others = > ' 0 ' ) , squareCnt = > ( others = > ' 0 ' ) , rampCnt = > ( others = > ' 0 ' ) , testData = > ( others = > ' 0 ' ) , inc = > ' 1 ' , sign = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/JesdTestStreamTx.vhd
• protocols/jesd204b/rtl/JesdTestStreamTx.vhd