SaciMaster2 Entity Reference

Inheritance diagram for SaciMaster2:

Collaboration diagram for SaciMaster2:

Entities
SaciMaster2.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
SYS_CLK_PERIOD_G	real := 8 . 0E - 9
SACI_CLK_PERIOD_G	real := 1 . 0E - 6
SACI_CLK_FREERUN_G	boolean := false
SACI_NUM_CHIPS_G	positive := 1
SACI_RSP_BUSSED_G	boolean := false

Ports
sysClk	in	sl
sysRst	in	sl
asicRstL	in	sl := ' 1 '
req	in	sl
ack	out	sl
fail	out	sl
chip	in	slv ( log2 ( SACI_NUM_CHIPS_G ) - 1 downto 0 )
op	in	sl
cmd	in	slv ( 6 downto 0 )
addr	in	slv ( 11 downto 0 )
wrData	in	slv ( 31 downto 0 )
rdData	out	slv ( 31 downto 0 )
saciClk	out	sl
saciSelL	out	slv ( SACI_NUM_CHIPS_G- 1 downto 0 )
saciCmd	out	sl
saciRsp	in	slv ( ite ( SACI_RSP_BUSSED_G , 0 , SACI_NUM_CHIPS_G- 1 ) downto 0 )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SaciMaster2.vhd
• protocols/saci/saci1/rtl/SaciMaster2.vhd