SaciMaster2.rtl Architecture Reference

Architecture >> SaciMaster2::rtl

Processes
comb	( addr , asicRstL , chip , cmd , op , r , req , saciRspSync , sysRst , wrData )
seq	( sysClk )
comb	( addr , asicRstL , chip , cmd , op , r , req , saciRspSync , sysRst , wrData )
seq	( sysClk )

Constants
SACI_CLK_HALF_PERIOD_C	integer := integer ( SACI_CLK_PERIOD_G/ ( 2 . 0 * SYS_CLK_PERIOD_G ) ) - 1
SACI_CLK_COUNTER_SIZE_C	integer := log2 ( SACI_CLK_HALF_PERIOD_C )
REG_INIT_C	RegType := ( state = > IDLE_S , shiftReg = > ( others = > ' 0 ' ) , shiftCount = > ( others = > ' 0 ' ) , asicRstL = > ( others = > ' 1 ' ) , clkCount = > ( others = > ' 0 ' ) , saciClkRising = > ' 0 ' , saciClkFalling = > ' 0 ' , ack = > ' 0 ' , fail = > ' 0 ' , rdData = > ( others = > ' 0 ' ) , saciClk = > ' 0 ' , saciSelL = > ( others = > ' 1 ' ) , saciCmd = > ' 0 ' )

Types
StateType	( IDLE_S , TX_S , RX_START_S , RX_HEADER_S , RX_DATA_S , ACK_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
saciRspSync	slv ( saciRsp )

Records
RegType

Instantiations
u_synchronizer_1	Synchronizer <Entity Synchronizer>
u_synchronizer_1	Synchronizer <Entity Synchronizer>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SaciMaster2.vhd
• protocols/saci/saci1/rtl/SaciMaster2.vhd