Ad9249ReadoutGroup Entity Reference

Inheritance diagram for Ad9249ReadoutGroup:

Collaboration diagram for Ad9249ReadoutGroup:

Entities
Ad9249ReadoutGroup.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>
Ad9249Pkg	Package <Ad9249Pkg>
vcomponents

Generics
TPD_G	time := 1 ns
NUM_CHANNELS_G	natural range 1 to 8 := 8
IODELAY_GROUP_G	string := " DEFAULT_GROUP "
IDELAYCTRL_FREQ_G	real := 200 . 0
DEFAULT_DELAY_G	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
ADC_INVERT_CH_G	slv ( 7 downto 0 ) := " 00000000 "
SIM_DEVICE_G	string := " ULTRASCALE "
D_DELAY_CASCADE_G	boolean := false
F_DELAY_CASCADE_G	boolean := false
USE_MMCME_G	boolean := false
SIM_SPEEDUP_G	boolean := false

Ports
axilClk	in	sl
axilRst	in	sl
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
adcClkRst	in	sl
adcSerial	in	Ad9249SerialGroupType
adcStreamClk	in	sl
adcStreams	out	AxiStreamMasterArray ( NUM_CHANNELS_G- 1 downto 0 ) := ( others = > axiStreamMasterInit ( ( false , 2 , 8 , 0 , TKEEP_NORMAL_C , 0 , TUSER_NORMAL_C ) ) )
adcBitClkIn	in	sl
adcBitClkDiv4In	in	sl
adcBitRstIn	in	sl
adcBitRstDiv4In	in	sl
adcReady	in	slv ( NUM_CHANNELS_G- 1 downto 0 ) := ( others = > ' 1 ' )

---

The documentation for this design unit was generated from the following files:

• devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ReadoutGroup.vhd
• devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd