GLinkGtp7FixedLat Entity Reference

Inheritance diagram for GLinkGtp7FixedLat:

Collaboration diagram for GLinkGtp7FixedLat:

Entities
GLinkGtp7FixedLat.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
GlinkPkg

Generics
FLAGSEL_G	boolean := false
SYNTH_TX_G	boolean := true
SYNTH_RX_G	boolean := true
TPD_G	time := 1 ns
SIM_GTRESET_SPEEDUP_G	string := " FALSE "
SIM_VERSION_G	string := " 4.0 "
SIMULATION_G	boolean := false
RXOUT_DIV_G	integer := 2
TXOUT_DIV_G	integer := 2
RX_CLK25_DIV_G	integer := 5
TX_CLK25_DIV_G	integer := 5
PMA_RSV_G	bit_vector := x " 00000333 "
RX_OS_CFG_G	bit_vector := " 0001111110000 "
RXCDR_CFG_G	bit_vector := x " 0000107FE206001041010 "
RXLPM_INCM_CFG_G	bit := ' 1 '
RXLPM_IPCM_CFG_G	bit := ' 0 '
TX_PLL_G	string := " PLL0 "
RX_PLL_G	string := " PLL1 "

Ports
gLinkTx	in	GLinkTxType
txReady	out	sl
gLinkTxClk	in	sl
gLinkTxClkEn	in	sl := ' 1 '
gLinkRx	out	GLinkRxType
rxReady	out	sl
gLinkRxClk	in	sl
gLinkRxClkEn	in	sl := ' 1 '
gLinkTxRefClk	in	sl
stableClk	in	sl
gtQPllRefClk	in	slv ( 1 downto 0 )
gtQPllClk	in	slv ( 1 downto 0 )
gtQPllLock	in	slv ( 1 downto 0 )
gtQPllRefClkLost	in	slv ( 1 downto 0 )
gtQPllReset	out	slv ( 1 downto 0 )
loopback	in	slv ( 2 downto 0 )
gtTxP	out	sl
gtTxN	out	sl
gtRxP	in	sl
gtRxN	in	sl

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The documentation for this design unit was generated from the following file:

• protocols/glink/gtp7/rtl/GLinkGtp7FixedLat.vhd