AxiStreamFrameRateLimiter Entity Reference

Inheritance diagram for AxiStreamFrameRateLimiter:

Collaboration diagram for AxiStreamFrameRateLimiter:

Entities
AxiStreamFrameRateLimiter.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
PIPE_STAGES_G	natural := 0
COMMON_CLK_G	boolean := false
BACKPRESSURE_G	boolean := false
AXIS_CLK_FREQ_G	real := 156 . 25E + 6
REFRESH_RATE_G	real := 1 . 0E + 0
DEFAULT_MAX_RATE_G	positive := 1

Ports
axisClk	in	sl
axisRst	in	sl
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType
mAxisCtrl	in	AxiStreamCtrlType := AXI_STREAM_CTRL_UNUSED_C
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamFrameRateLimiter.vhd
• build/SRC_VHDL/surf/AxiStreamFrameRateLimiter.vhd