AxiStreamFrameRateLimiter.rtl Architecture Reference

Architecture >> AxiStreamFrameRateLimiter::rtl

Processes
comb	( axisRst , backpressure , mAxisCtrl , r , rateLimit , sAxisMaster , txSlave )
seq	( axisClk , axisRst )
comb	( axisRst , backpressure , mAxisCtrl , r , rateLimit , sAxisMaster , txSlave )
seq	( axisClk , axisRst )

Constants
TIMEOUT_C	natural := getTimeRatio ( AXIS_CLK_FREQ_G , REFRESH_RATE_G ) - 1
BACKPRESSURE_C	slv ( 31 downto 0 ) := ite ( BACKPRESSURE_G , x " 0000_0001 " , x " 0000_0000 " )
INI_WRITE_REG_C	Slv32Array ( 1 downto 0 ) := ( 0 = > toSlv ( DEFAULT_MAX_RATE_G , 32 ) , 1 = > BACKPRESSURE_C )
REG_INIT_C	RegType := ( tValid = > ' 0 ' , rateLimit = > ( others = > ' 0 ' ) , frameCnt = > ( others = > ' 0 ' ) , timer = > 0 , sAxisSlave = > AXI_STREAM_SLAVE_INIT_C , txMaster = > AXI_STREAM_MASTER_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , MOVE_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
txSlave	AxiStreamSlaveType
readReg	Slv32Array ( 2 downto 0 )
writeReg	Slv32Array ( 1 downto 0 )
rateLimit	slv ( 31 downto 0 )
backpressure	sl

Records
RegType

Instantiations
u_axiliteregs	AxiLiteRegs <Entity AxiLiteRegs>
u_ratelimit	SynchronizerVector <Entity SynchronizerVector>
u_backpressure	Synchronizer <Entity Synchronizer>
u_axistreampipeline	AxiStreamPipeline <Entity AxiStreamPipeline>
u_axiliteregs	AxiLiteRegs <Entity AxiLiteRegs>
u_ratelimit	SynchronizerVector <Entity SynchronizerVector>
u_backpressure	Synchronizer <Entity Synchronizer>
u_axistreampipeline	AxiStreamPipeline <Entity AxiStreamPipeline>

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamFrameRateLimiter.vhd
• build/SRC_VHDL/surf/AxiStreamFrameRateLimiter.vhd