AxiLiteRegs Entity Reference

Inheritance diagram for AxiLiteRegs:

Entities
AxiLiteRegs.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
NUM_WRITE_REG_G	integer range 1 to 32 := 1
INI_WRITE_REG_G	Slv32Array := ( 0 = > x " 0000_0000 " )
NUM_READ_REG_G	integer range 1 to 32 := 1

Ports
axiClk	in	sl
axiClkRst	in	sl
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
writeRegister	out	Slv32Array ( NUM_WRITE_REG_G- 1 downto 0 )
readRegister	in	Slv32Array ( NUM_READ_REG_G- 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )

---

The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteRegs.vhd
• build/SRC_VHDL/surf/AxiLiteRegs.vhd