AxiLiteRegs.rtl Architecture Reference

Architecture >> AxiLiteRegs::rtl

Functions
WriteRegArray	writeRegIni ( iniVal: in Slv32Array )
WriteRegArray	writeRegIni ( iniVal: in Slv32Array )

Processes
comb	( axiClkRst , axiReadMaster , axiWriteMaster , r , readRegister )
seq	( axiClk , axiClkRst )
comb	( axiClkRst , axiReadMaster , axiWriteMaster , r , readRegister )
seq	( axiClk , axiClkRst )

Constants
REG_INIT_C	RegType := ( writeRegister = > writeRegIni ( INI_WRITE_REG_G ) , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Subtypes
WriteRegArray	Slv32Array ( writeRegister )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteRegs.vhd
• build/SRC_VHDL/surf/AxiLiteRegs.vhd